1. Field of the Invention
The present invention relates to a semiconductor memory having an error correction function.
2. Description of the Related Art
In a semiconductor memory having an error correction function, a technology that decreases the number of signal lines through which sub parity data are transferred has been proposed (for example, Japanese Unexamined Patent Application Publication No. Sho 62-119800). In this technology, sub parity data of read data are generated for each memory block. The sub parity data are successively combined. Thereafter, parity data are generated.
When parity data are generated by successively combining sub parity data, a plurality of parity generation circuits (parity verification circuits) are needed to combine sub parity data. Thus, the layout design, layout verification, and so forth of the semiconductor memory become complicated.